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Language/Verilog & SV

[Verilog & SV] 논리 연산자(Logical Operators)

by VIR&US 2025. 4. 9.
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    Logical Operators

    a = 3’b010 b = 3’b000

    Character
    Operation performed
    Example
    Type
    !
    Logical negation
    !(a && b) = 1’b1
    Unary
    &&
    Logical and (both
    expressions true)
    a && b = 1’b0
    Binary
    ||
    Logical or (One or both
    expressions true)
    a || b = 1’b1
    Binary
    ->
    Logical implication
    exp1 -> exp2 is same with
    (!exp1 || exp2)
    Binary
    <->
    Logical equivalence
    exp1 <-> exp2 is same with
    ((exp1->exp2)&&(exp2->exp1))
    Unary

    Logical implication

    Implication ( p -> q ) [= (!p || q)]

    • p가 F이거나, q가 T이거나
    p
    q
    p -> q
    T
    T
    T
    T
    F
    F
    F
    T
    T
    F
    F
    T

    Equivalence ( p <-> q ) [= ((p -> q) && (q -> p))]

    • p가 F이고 q가 F
    • p가 T이고 q가 T
    p
    q
    p -> q
    T
    T
    T
    T
    F
    F
    F
    T
    F
    F
    F
    T

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