[Verilog & SV] 관계 연산자(Relational Operators)

 

• 피연산자를 비교하여 1비트 scalar boolean value을 산출합니다.
• 비트 크기가 서로 다르면 더 작은 피연산자가 0으로 확장됩니다.

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a = 3’b01 b = 3’b100 c = 3’b111 d = 3’b01z e = 3’b01x

Character	Operation performed	Example	Type
>	Greater than	a > b = 1’b0	Binary
<	Smaller than	a < b = 1’b1	Binary
>=	Greater than or equal	a >= d = 1’bX	Binary
<=	Smaller than or equal	a <= e = 1’bX	Binary
==	Logical equality	a == b = 1’b0	Binary
!=	Logical inequality	a != b = 1’b1 b != e = 1’bx	Binary
===	Case (x, z) equality	e === e = 1’b1	Binary
!===	Case (x, z) inequality	a !== d = 1’b1	Binary
==? !=?	comparison with wildcard	dout = (din ==? 4’b???0);	Binary