[Verilog & SV] Bitwise, 감소 연산자(Reduction Operators)

목차

Reduction Operator

• Reduction Operator들은 벡터를 단 하나의 비트로만 줄입니다.
• Bitwise 연산입니다.
• If there are the characters Z and X, the result can be a known value.

Example

​ a = 5’b10101 b = 4’b0011 c = 3’bz00 d = 3’bx011

Character	Operation performed	Example	Type
&	And all bits	&a = 1’b0, &d = 1’b0	Unary
~&	Nand all bits	~&a = 1’b1	Unary
|	Or all bits	|a = 1’b1, |c = 1’bX	Unary
~|	Nor all bits	~|a= 1’b0	Unary
^	Xor all bits	^a = 1’b1	Unary
^~ ~^	Xnor all bits	~^a = 1’b0	Unary

Code example

reg[7:0] cnt;     assign parity = ^cnt;     assign parity = cnt[7]^cnt[6]^cnt[5]^cnt[4]^cnt[3]^cnt[2]^cnt[1]^cnt[0];