[System Verilog] 'break' and 'continue'

목차

break

loop construct에서 break를 만나면 바로 end로 진입합니다.

 

Code

module tb;	
	initial begin
     	// This for loop increments i from 0 to 9 and exit
    		for (int i = 0 ; i < 10; i++) begin
        		$display ("Iteration [%0d]", i);
        		if (i == 7)begin
          			break;
        		end
      		end
    	end
endmodule

Sim

ncsim> run
Iteration [0]
Iteration [1]
Iteration [2]
Iteration [3]
Iteration [4]
Iteration [5]
Iteration [6]
Iteration [7]
ncsim: *W,RNQUIE: Simulation is complete.

---

continue

loop construct에서 continue를 만나면 하단의 작업을 완료하지 않고 다시 loop construct로 진입합니다.

 

Code

module tb;
	initial begin
      	// This for loop increments i from 0 to 9 and exit
		for (int i = 0 ; i < 10; i++) begin
		        if (i == 7) begin
          			continue;
			end
        		$display ("Iteration [%0d]", i);
      		end
    	end
endmodule

Sim

ncsim> run
Iteration [0]
Iteration [1]
Iteration [2]
Iteration [3]
Iteration [4]
Iteration [5]
Iteration [6]
Iteration [8]
Iteration [9]
ncsim: *W,RNQUIE: Simulation is complete.