[Verilog] Ram Model example Code

Ram Model

간단한 Ram Verilog Code입니다. simulation model로 사용할 수 있습니다.

 

A는 Write port 

• CLK_A, addr_A, data_A, WENA
• CLK_A가 posedge일때, WENA == 1이면 addr_A에 해당하는 메모리 공간에 data_A를 씁니다.

B는 Read port

• CLK_B, addr_B, data_B
• CLK_B가 posedge일때, addr_B에 해당하는 메모리 공간을 읽어 data_B로 출력합니다.

 

Verilog Model Code

 

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////////////////////////////// //Random Access Memory (RAM)// ////////Simple DPRAM////////// ////1p Read(B), 1p Wirte(A)/// ////////////////////////////// module RAM (CLK_A, addr_A, data_A, WENA, CLK_B, addr_B, data_B); parameter D_WIDTH = 16; parameter A_WIDTH = 4; // Write port input CLK_A; input [A_WIDTH-1:0] addr_A; input [D_WIDTH-1:0] data_A; input WENA; // Read port input CLK_B; input [A_WIDTH-1:0] addr_B; output [D_WIDTH-1:0] data_B; reg [D_WIDTH-1:0] data_B; // Memory as multi-dimensional array reg [D_WIDTH-1:0] memory [2**A_WIDTH-1:0]; // Write data to memory always @(posedge CLK_A) begin if (WENA) begin memory[addr_A] <= data_A; end end // Read data from memory always @(posedge CLK_B) begin data_B <= memory[addr_B]; end endmodule

 

Verilog testbech Code

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////////////////////////////// //Random Access Memory (RAM)// ////////Simple DPRAM////////// ////1p Read(B), 1p Wirte(A)/// ////////////////////////////// // Testbench module test; reg CLK_A; reg [7:0] addr_A; reg [15:0] data_A; reg WENA; reg CLK_B; reg [7:0] addr_B; wire [15:0] data_B; // Instantiate design under test // D_WIDTH = 16 // A_WIDTH = 8 RAM #(16, 8) RAM ( .CLK_A(CLK_A), .addr_A(addr_A), .data_A(data_A), .WENA(WENA), .CLK_B(CLK_B), .addr_B(addr_B), .data_B(data_B)); initial begin // Dump waves $dumpfile("dump.vcd"); $dumpvars(0, test); CLK_A = 0; CLK_B = 0; WENA = 0; addr_B = 8'h12; addr_A = addr_B; $display("Read data, addr %h.",addr_B); toggle_CLK_B; $display("data[%0h]: %0h", addr_B, data_B); $display("Write new data."); WENA = 1; data_A = $random; toggle_CLK_A; WENA = 0; $display("Read new data."); toggle_CLK_B; $display("data[%0h]: %0h", addr_B, data_B); end task toggle_CLK_A; begin #10 CLK_A = ~CLK_A; #10 CLK_A = ~CLK_A; end endtask task toggle_CLK_B; begin #10 CLK_B = ~CLK_B; #10 CLK_B = ~CLK_B; end endtask endmodule

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https://www.edaplayground.com/x/taV_ 

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