[Verilog] 1bit Half adder(반가산기)

목차

• 목차
• Half adder
  • Code
  • Gate Primitive Code

Half adder

1비트 이진수 두 개를 더한 합 Sum (S)과 자리올림 수 Carry (C)를 구하는 회로

source: raspberrypi.org

Code

module half_adder (
  input A,
  input B,
  output Sum,
  output Carry);

  assign Carry = A & B;
  assign Sum = A ^ B;

endmodule

Gate Primitive Code

module half_adder (
  input A,
  input B,
  output Sum,
  output Carry);

  xor (Sum, A, B);
  and (Carry, A, B);

endmodule